@instlatx64.bsky.socialThe most important question is whether #Intel #CoyoteCove / #PantherCove inherited this ZMM-issue from the earlier *Coves; if not, that represents a significant advantage, since, as we know, "the least interesting part of #AVX512 is the 512-bit vector width.":
mastodon.gamedev.place/@rygorous/11...
@instlatx64.bsky.socialThis #AVX512 implementation suggests that the 6 FPU port in #CoyoteCove delivers 6x256b / 3x512b peak FP performance, which is +50% compared to single-chip mobile #AMD #Zen6 #Medusa (4x256b) and -25% compared to desktop #Zen6 #OlympicRidge (4x512b).
@instlatx64.bsky.socialDeobfuscated #Intel #LionCove block diagram reveals further #AVX512 implementation details.
According to PMCs, V0 = V1 and V2 = V3 pipes are almost(*) completely identical.
This hints that 512b zmm operands are executed in V0+V1, V2+V3 pairs.
#CougarCove #CoyoteCove
