The most important question is whether #Intel #CoyoteCove / #PantherCove inherited this ZMM-issue from the earlier *Coves; if not, that represents a significant advantage, since, as we know, "the least interesting part of #AVX512 is the 512-bit vector width.":
mastodon.gamedev.place/@rygorous/11...

Of course this means also that the desktop #NovaLake 300F1x and mobile #NovaLakeL 300F3x has +50% peak vector performance advantage over the dual-512b-issue #SkyLakeX, #IceLakeX, #SapphireRapids, #EmeraldRapids, #GraniteRapids
#AVX512 #AVX10_1 #AVX10_2

This #AVX512 implementation suggests that the 6 FPU port in #CoyoteCove delivers 6x256b / 3x512b peak FP performance, which is +50% compared to single-chip mobile #AMD #Zen6 #Medusa (4x256b) and -25% compared to desktop #Zen6 #OlympicRidge (4x512b).

#Intel perf + #NovaLake:
bsky.app/profile/inst...

#AMD released the "AMD EPYC SERVER CPU ARCHITECTURE AND PERFORMANCE OVERVIEW" White Paper:
www.amd.com/content/dam/...
#Zen6 #Zen6c #AVX512 #x86EAG #EAG #ACE

Deobfuscated #Intel #LionCove block diagram reveals further #AVX512 implementation details.
According to PMCs, V0 = V1 and V2 = V3 pipes are almost(*) completely identical.
This hints that 512b zmm operands are executed in V0+V1, V2+V3 pairs.
#CougarCove #CoyoteCove