@philpem.digipres.club.ap.brid.gyThe more I play with this idea of a Verilog reimplementation of an Inmos T425 #transputer, the more I realise I'm just restating the microcode in different syntax.
With that said, it's made it easier to change the microsequencer and play with FPGA DSP blocks and barrel shifters. If you're […]
@philpem.digipres.club.ap.brid.gyI decided I'd take a look at implementing an Inmos #Transputer (T425 specifically) core in Verilog. The fetch-execute and ALU stages were not awful. Now I'm getting into the (hardware!) task scheduler, channel controller and DMA blocks (FOUR OF THEM) and I'm regretting my life choices.
@nanochess.bsky.socialDo you remember my DJGPP port of my transputer C compiler? I thought all the work was done, and maybe I could compile it in a Macbook Air. I was very wrong. Enjoy my trip porting it to 64-bit!!! #retro #transputer nanochess.org/transputer_c...
@nanochess.bsky.socialDo you remember my DJGPP port of my transputer C compiler? I thought all the work as done, and maybe I could compile it in a Macbook Air. I was very wrong. Enjoy my trip porting it to a 64-bit!!! #retro #transputer nanochess.org/transputer_c...
@nanochess.mastodon.social.ap.brid.gyDo you remember my DJGPP port of my transputer C compiler? I thought all the work was done, and maybe I could compile it in a Macbook Air. I was very wrong. Enjoy my trip porting it to 64-bit!!! #retro #transputer https://nanochess.org/transputer_c_compiler.html