@edsonbellido.bsky.social2/4 MRAM stores bits in magnetic tunnel junctions, not charge levels. Nonvolatile, byte addressable, DRAM class speed in the tens of nanoseconds, huge endurance. Write metadata persists through power loss. No cap discharge, no emergency flush to NAND. #MRAM #Chips
@edsonbellido.bsky.social1/4 IBM's gen 5 FlashCore SSDs dropped supercapacitors for power loss protection. Everspin MRAM now holds write metadata through outages. A quiet board redesign with real capacity payoff 🧵 #SSD #MRAM
![SemiRecap Infographic [HARDWARE_DEEP_DIVE]: IBM Deploys Everspin MRAM in Gen 5 FlashCore. A stylized 2.5D vector cartoon illustration on solid white background (#FFFFFF) showing an IBM FCM5 SSD board with a large AMD processor die at center and a small Everspin MRAM chip at the top right with warm gold pins, connected by cyan bus traces to dense QLC NAND dies and a slim SLC incoming write zone. A lightning bolt power loss icon strikes the board while a glowing MRAM cell retains metadata bits, and an empty dashed outline where supercapacitors once sat is labeled 'SUPERCAP SPACE RECLAIMED FOR NAND'. Deep Maroon (#450d16) chip bodies, amber gold traces, minimal clean structural labels.](https://cdn.bsky.app/img/feed_fullsize/plain/did:plc:nxdiuv7626cjwxguzjlh4o3b/bafkreid34ieu7tx3p7re6mell64ve4c5ew5yx4pe7m3ib2qjjnevkca5i4@png)
@edsonbellido.bsky.social4/4 Source: Blocks & Files (Oct 1, 2026): Everspin demos CXL connected MRAM memory expansion. https://www.blocksandfiles.com/architecture/2026/10/01/everspin-demos-cxl-connected-mram-memory-expansion/5300563 #Semiconductors #CXL #MRAM
@edsonbellido.bsky.social1/4 MRAM has DRAM speed, NAND persistence, and a price tag that kept it niche for years. Everspin just wired it to an x86 server over CXL. Does that change the memory tier math for AI inference? 🧵 #Semiconductors #MRAM
![SemiRecap Infographic [HARDWARE_DEEP_DIVE]: Everspin Demos CXL MRAM Memory Expansion. A 2.5D vector cartoon tech illustration on solid pure white background (#FFFFFF). Left side: a maroon Supermicro x86 server chassis labeled 'X86 HOST SERVER' with a visible CPU block labeled 'AMD EPYC 9355'. A cyan bus trace labeled 'PCIE GEN3 X8 / CXL 3.2' runs from the server to a maroon expansion card labeled 'ALVEO U250 FPGA' carrying a smaller maroon silicon block labeled 'WOLLEY CXL 3.2 CONTROLLER' and four vertical gold pinned DIMM slots labeled '4X PERSYST MRAM UDIMM (1GB)'. A subtle glow around the DIMMs represents the persistent cache tier holding KV cache blocks. Deep Maroon (#450d16) chip bodies, warm gold pins, cyan bus traces, minimal clean structural labels.](https://cdn.bsky.app/img/feed_fullsize/plain/did:plc:nxdiuv7626cjwxguzjlh4o3b/bafkreiau5g2g4fjiog6ivk3duqigdth722jav66wsjjia7vmuz523gkkci@png)
@stocktitan.net#MRAM Everspin Technologies to Ring Opening Bell in Celebration of 10-Year Nasdaq Anniversary
@magnetism.eu#event 18th #MRAM Global #Innovation #Forum buff.ly/kIwhFSB 17 Dec 2026; San Francisco, CA, USA. 1 day after IEDM conference
@magnetism.eu#event What is #STT-#MRAM? 5 Oct 2026; 8 pm CET buff.ly/x8V7zEi #online #industry #webinar
@stocktitan.net#MRAM Everspin Demonstrates World’s First CXL-Connected MRAM at SNIA Developer Conference 2026
@new3rd.bsky.social