4/4 Source: Blocks & Files (Oct 1, 2026): Everspin demos CXL connected MRAM memory expansion. https://www.blocksandfiles.com/architecture/2026/10/01/everspin-demos-cxl-connected-mram-memory-expansion/5300563 #Semiconductors #CXL #MRAM

3/4 The pitch: KV cache blocks for edge AI inference that survive power loss without battery backed DRAM or an SSD flush. But Gen3 bandwidth is the constraint. Would you spec CXL attached MRAM at today's price, or wait for Gen5 links? #CXL #AIInference

2/4 The stack: Supermicro AS-1116CS-TN + AMD EPYC 9355, an Alveo U250 FPGA running Wolley CXL 3.2 controller IP, and 4x 1GB PERSYST STT MRAM UDIMMs. Carrier: PCIe Gen3 x8. Writes up to 100x faster than NAND SSDs, nanosecond class cache line access. #CXL #AIHardware

Samsung targets KV cache constraints by combining its CMM-D modules with solid state drives and memory-proximate processing, leaning heavily on dedicated software management. #Memory #CXL