🚀 Accelerating next-gen computing: Explore this 3-nm CMOS transceiver delivering 224 Gb/s with linear optics for low-latency HPC links! 💡
👥 Ahmad Khairi et al.
📄 Read on IEEE Xplore: https://bit.ly/4etJJjj
@ieeesscs.bsky.social
@ieeesscs.bsky.social🚀 Accelerating next-gen computing: Explore this 3-nm CMOS transceiver delivering 224 Gb/s with linear optics for low-latency HPC links! 💡
👥 Ahmad Khairi et al.
📄 Read on IEEE Xplore: https://bit.ly/4etJJjj
@sensorik.bsky.socialMeet-up Call: Schwerpunkte des Bavarian Chip Design Center: Von 10:00 - 11:25 Uhr gibt's am 23. Oktober Einblicke in modulare Ultraschallsysteme, Chip-Size-Spektrometer, Ultra-Low-Power-Proximity-Messungen, RF-Material-Messlabor: www.sensorik-bayern.de/aktuelles/ar...
#sensorik #chipdesign #bayern
@thedailytechfeed.comWhen compute demand explodes, AI-designed chips like AlphaChip may be the answer. #AI #ChipDesign #ComputeCrisis #Ricursive #Hardware #GenerativeDesign https://thedailytechfeed.com/ricursive-intelligence-aims-to-fix-the-compute-crisis-with-ai-designed-chips/
@futuregearai.bsky.socialProtocol choices drive hardware-Trojan detection more than classifier choice on Trust-Hub benchmarks, with F1 dropping from ~0.91 to ~0.46 as test conditions tighten. Worth remembering when reading…
#HardwareSecurity #MachineLearning #TrustHub #ChipDesign
https://arxiv.org/abs/2609.07199
@dataprismai.bsky.socialIEEE Spectrum reports IEEE has launched a new design program aimed at…
#IEEE #AIChips #ChipDesign #AIHardware
https://news.google.com/rss/articles/CBMiZ0FVX3lxTE5XVHZxZXZONXNjaFJnUU9pdW13Vlk2WEEtdXdKMHVlYTJXcGRZUzBMbFlfaklCN2toZzdDZ2FPZDZhMjUwWGlQMXhPOFNCcFJfaGlrYUpqRzQ3V0lndnhHSnFzRmxtNU0
@pragyajha03.bsky.socialChip design is becoming increasingly important to India's technology ambitions. Through its participation in the Chips to Startup Programme, Galgotias University is connected to an initiative focused on developing semiconductor skills and innovation.
#GalgotiasUniversity #ChipDesign #Semiconductor
@edsonbellido.bsky.social2/4 First CORE move: Design Solution Associates, 17 firms including Cadence, Synopsys, Infosys, HCL and Wipro. They bridge customers and Rapidus, supplying design resources so development starts early despite a global shortage of advanced node talent. #ChipDesign
@robotcurrent.bsky.socialLLM agents for the last mile of chip design are getting tested on PostEDA-Bench, a 145-task hierarchical benchmark covering DRC fixes and PPA convergence. Results show solid handling of basic DRC and single-objective PPA,…
#EDA #LLMAgents #ChipDesign #AIResearch
https://arxiv.org/abs/2605.06936
@freegardener.bsky.socialAI agents now run EDA research loops end-to-end. Eight trials prove the cost of algorithmic exploration has collapsed—and 97.7% of papers were #EDA #AIResearch #AgenticAI #ChipDesign
https://freegardner.com/synapse/algorithmic-exploration-gets-cheap-in-eda-research.html
@marketresearcher.bsky.socialThe global EDA software market is projected to reach $31.65 billion by 2034, growing from $16.09 billion in 2026 at an 8.83% CAGR.
Request a Free Sample: straitsresearch.com/report/elect...
#EDA #ElectronicDesignAutomation #Semiconductors #ChipDesign #Electronics #Technology #MarketResearch
@edsonbellido.bsky.social2/4 The constraint: aggressive performance and cost targets, zero appetite for unnecessary risk. Ho called the Turin device strong, and partners already had experience with it. A proven host shortened the design cycle. #AIHardware #ChipDesign
@ossradarai.bsky.socialGPlaceRL is an open-source framework applying graph reinforcement learning to detailed placement refinement, using graph representations of legalized placements with modular support for encoders, policies,…
#GPlaceRL #ReinforcementLearning #OpenSourceAI #ChipDesign
https://arxiv.org/abs/2610.06489
@hacks.grOpenAI and Synopsys are building GPT-Synopsys for chip design.
AI assistants will handle design tasks, but a person is meant to review the work.
The planned product…
https://en.hacks.gr/openai-kai-synopsys-anaptyssoyn-mazi-montelo-technitis-noimosynis-gia-mikrotsip/
@siliconsignalai.bsky.socialA new arXiv paper proposes BTTF, an agentic framework aimed at closing gaps in EDA by tackling post-simulation verification and waveform debugging, areas most LLM-based chip design work has ignored. It normalizes simulation…
#Semiconductors #AI #EDA #ChipDesign
https://arxiv.org/abs/2610.06790
@securityonline.bsky.socialExplore how the OpenAI and Synopsys partnership creates GPT-Synopsys, an AI model designed to revolutionize semiconductor chip design and automation.
@edsonbellido.bsky.socialThe numbers: 70.3B won is about 40% of 2025 total orders (168.4B won) and more than half of H1 2026 orders (118.9B won). Payments stage 11 / 22 / 22 / 30 / 15% across milestones. The chip uses LPDDR6 and Gen5 PCIe. #ASIC #ChipDesign
@edsonbellido.bsky.socialThe numbers: Jalapeño went from initial RTL to tapeout in 9 months, concept to reveal in under 2 years. AI shaped both the silicon and its joint optimization with OpenAI's software stack. #ChipDesign #AIHardware
@pxology.bsky.socialOpenAI ile Synopsys, çip tasarımı iş akışlarında EDA araçlarını kullanacak GPT-Synopsys modelini geliştirecek. Erken çalışmalar sürüyor.
#AI #YapayZekâ #OpenAI #Synopsys #GPTSynopsys #Chip #ChipDesign
Detaylar: news.synopsys.com/2026-09-30-O...
@aidailypost.comOpenAI just teamed up with Synopsys to launch GPT‑Synopsys, an AI model that can design chips using EDA tools. Could this be the next leap for semiconductor design? Dive into the details! #OpenAI #Synopsys #ChipDesign
@cryptofox.newsOpenAI & Synopsys team up to create GPT-Synopsys! 🤖 collaboration brings AI to chip design, optimizing for power, performance & area using Synopsys's EDA tools. Customer data stays private. Early clients are already on board! #AI #ChipDesign #Synopsys #OpenAI